U.S. Pat. No. 5,502,747 entitled “Method and apparatus for filtering an electronic environment with improved accuracy and efficiency and short flow-through delay” filed by the present applicant, discloses a convolution filter having low latency and also having the ability to perform long convolutions.
Modern DSP algorithms are normally implemented on a digital signal processor such as the Motorola 56300 family, or (increasingly often) on general purpose microprocessors or custom or field-programmable integrated circuits (ASICs or FPGAs). Modern processor architectures normally have limited on-board memory resources and, as such, these resources must be managed efficiently, especially when off-chip memory access often incurs a relatively high overhead penalty, in that “wait states” are often incurred.
A wait-state is a processor state in which the processing element does nothing while it waits for a value to be read from or written to external memory. There may be more than one wait-state associated with each off-chip memory access. It is a characteristic of typical on-board memory systems that they induce fewer wait-states than off-chip memory, or none.
It would therefore be desirable to provide for an efficient form of convolution process which is amenable to a high speed implementation on such processor architectures.